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stm32f4xx_adc.h ( 文件浏览 )

  • zhyunhao 发布于2015-01-04
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			/**
  ******************************************************************************
  * @file    stm32f4xx_adc.h
  * @author  MCD Application Team
  * @version V1.0.0
  * @date    30-September-2011
  * @brief   This file contains all the functions prototypes for the ADC firmware 
  *          library.
  ******************************************************************************
  * @attention
  *
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  *
  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
  ******************************************************************************
  */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_ADC_H
#define __STM32F4xx_ADC_H

#ifdef __cplusplus
 extern "C" {

#endif

/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx.h"

/** @addtogroup STM32F4xx_StdPeriph_Driver
  * @{

  */

/** @addtogroup ADC
  * @{

  */ 

/* Exported types ------------------------------------------------------------*/

/** 
  * @brief   ADC Init structure definition  
  */ 
typedef struct
{

  uint32_t ADC_Resolution;                /*!< Configures the ADC resolution dual mode. 
                                               This parameter can be a value of @ref ADC_resolution */                                   
  FunctionalState ADC_ScanConvMode;       /*!< Specifies whether the conversion 
                                               is performed in Scan (multichannels) 
                                               or Single (one channel) mode.
                                               This parameter can be set to ENABLE or DISABLE */ 
  FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion 
                                               is performed in Continuous or Single mode.
                                               This parameter can be set to ENABLE or DISABLE. */
  uint32_t ADC_ExternalTrigConvEdge;      /*!< Select the external trigger edge and
                                               enable the trigger of a regular group. 
                                               This parameter can be a value of 
                                               @ref ADC_external_trigger_edge_for_regular_channels_conversion */
  uint32_t ADC_ExternalTrigConv;          /*!< Select the external event used to trigger 
                                               the start of conversion of a regular group.
                                               This parameter can be a value of 
                                               @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */
  uint32_t ADC_DataAlign;                 /*!< Specifies whether the ADC data  alignment
                                               is left or right. This parameter can be 
                                               a value of @ref ADC_data_align */
  uint8_t  ADC_NbrOfConversion;           /*!< Specifies the number of ADC conversions
                                               that will be done using the sequencer for
                                               regular channel group.
                                               This parameter must range from 1 to 16. */

}ADC_InitTypeDef;
  
/** 
  * @brief   ADC Common Init structure definition  
  */ 
typedef struct 
{

  uint32_t ADC_Mode;                      /*!< Configures the ADC to operate in 
                                               independent or multi mode. 
                                               This parameter can be a value of @ref ADC_Common_mode */                                              
  uint32_t ADC_Prescaler;                 /*!< Select the frequency of the clock 
                                               to the ADC. The clock is common for all the ADCs.
                                               This parameter can be a value of @ref ADC_Prescaler */
  uint32_t ADC_DMAAccessMode;             /*!< Configures the Direct memory access 
                                              mode for multi ADC mode.
                                               This parameter can be a value of 
                                               @ref ADC_Direct_memory_access_mode_for_multi_mode */
  uint32_t ADC_TwoSamplingDelay;          /*!< Configures the Delay between 2 sampling phases.
                                               This parameter can be a value of 
                                               @ref ADC_delay_between_2_sampling_phases */
  

}ADC_CommonInitTypeDef;


/* Exported constants --------------------------------------------------------*/

/** @defgroup ADC_Exported_Constants
  * @{

  */ 
#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
                                   ((PERIPH) == ADC2) || \
                                   ((PERIPH) == ADC3))  

/** @defgroup ADC_Common_mode 
  * @{

  */ 
#define ADC_Mode_Independent                       ((uint32_t)0x00000000)       
#define ADC_DualMode_RegSimult_InjecSimult         ((uint32_t)0x00000001)
#define ADC_DualMode_RegSimult_AlterTrig           ((uint32_t)0x00000002)
#define ADC_DualMode_InjecSimult                   ((uint32_t)0x00000005)
#define ADC_DualMode_RegSimult                     ((uint32_t)0x00000006)
#define ADC_DualMode_Interl                        ((uint32_t)0x00000007)
#define ADC_DualMode_AlterTrig                     ((uint32_t)0x00000009)
#define ADC_TripleMode_RegSimult_InjecSimult       ((uint32_t)0x00000011)
#define ADC_TripleMode_RegSimult_AlterTrig         ((uint32_t)0x00000012)
#define ADC_TripleMode_InjecSimult                 ((uint32_t)0x00000015)
#define ADC_TripleMode_RegSimult                   ((uint32_t)0x00000016)
#define ADC_TripleMode_Interl                      ((uint32_t)0x00000017)
#define ADC_TripleMode_AlterTrig                   ((uint32_t)0x00000019)
#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
                           ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \
                           ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \
                           ((MODE) == ADC_DualMode_InjecSimult) || \
                           ((MODE) == ADC_DualMode_RegSimult) || \
                           ((MODE) == ADC_DualMode_Interl) || \
                           ((MODE) == ADC_DualMode_AlterTrig) || \
                           ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \
                           ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \
                           ((MODE) == ADC_TripleMode_InjecSimult) || \
                           ((MODE) == ADC_TripleMode_RegSimult) || \
                           ((MODE) == ADC_TripleMode_Interl) || \
                           ((MODE) == ADC_TripleMode_AlterTrig))
/**
  * @
}
  */ 


/** @defgroup ADC_Prescaler 
  * @{

  */ 
#define ADC_Prescaler_Div2                         ((uint32_t)0x00000000)
#define ADC_Prescaler_Div4                         ((uint32_t)0x00010000)
#define ADC_Prescaler_Div6                         ((uint32_t)0x00020000)
#define ADC_Prescaler_Div8                         ((uint32_t)0x00030000)
#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \
                                     ((PRESCALER) == ADC_Prescaler_Div4) || \
                                     ((PRESCALER) == ADC_Prescaler_Div6) || \
                                     ((PRESCALER) == ADC_Prescaler_Div8))
/**
  * @
}
  */ 


/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode 
  * @{

  */ 
#define ADC_DMAAccessMode_Disabled      ((uint32_t)0x00000000)     /* DMA mode disabled */
#define ADC_DMAAccessMode_1             ((uint32_t)0x00004000)     /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
#define ADC_DMAAccessMode_2             ((uint32_t)0x00008000)     /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
#define ADC_DMAAccessMode_3             ((uint32_t)0x0000C000)     /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
                                      ((MODE) == ADC_DMAAccessMode_1) || \
                                      ((MODE) == ADC_DMAAccessMode_2) || \
                                      ((MODE) == ADC_DMAAccessMode_3))
                                     
/**
  * @
}
  */ 


/** @defgroup ADC_delay_between_2_sampling_phases 
  * @{

  */ 
#define ADC_TwoSamplingDelay_5Cycles               ((uint32_t)0x00000000)
#define ADC_TwoSamplingDelay_6Cycles               ((uint32_t)0x00000100)
#define ADC_TwoSamplingDelay_7Cycles               ((uint32_t)0x00000200)
#define ADC_TwoSamplingDelay_8Cycles               ((uint32_t)0x00000300)
#define ADC_TwoSamplingDelay_9Cycles               ((uint32_t)0x00000400)
#define ADC_TwoSamplingDelay_10Cycles              ((uint32_t)0x00000500)
#define ADC_TwoSamplingDelay_11Cycles              ((uint32_t)0x00000600)
#define ADC_TwoSamplingDelay_12Cycles              ((uint32_t)0x00000700)
#define ADC_TwoSamplingDelay_13Cycles              ((uint32_t)0x00000800)
#define ADC_TwoSamplingDelay_14Cycles              ((uint32_t)0x00000900)
#define ADC_TwoSamplingDelay_15Cycles              ((uint32_t)0x00000A00)
#define ADC_TwoSamplingDelay_16Cycles              ((uint32_t)0x00000B00)
#define ADC_TwoSamplingDelay_17Cycles              ((uint32_t)0x00000C00)
#define ADC_TwoSamplingDelay_18Cycles              ((uint32_t)0x00000D00)
#define ADC_TwoSamplingDelay
...
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mpu6050.crf470.47 kB2014-02-20|22:47
mpu6050.d3.05 kB2014-02-20|22:47
mpu6050.o510.14 kB2014-02-20|22:47
mpu6050.__i985.00 B2014-02-20|22:47
ms5611.crf455.11 kB2014-09-30|11:21
ms5611.d2.91 kB2014-09-30|11:21
ms5611.o499.88 kB2014-09-30|11:21
osqmem.crf420.87 kB2014-09-30|11:22
osqmem.d1.82 kB2014-09-30|11:22
osqmem.o443.41 kB2014-09-30|11:22
pid.crf3.46 kB2014-09-30|11:22
pid.d84.00 B2014-09-30|11:22
pid.o24.76 kB2014-09-30|11:22
pwm_input.crf420.54 kB2014-09-30|11:21
pwm_input.d1.99 kB2014-09-30|11:21
pwm_input.o453.93 kB2014-09-30|11:21
pwm_output.crf458.55 kB2014-09-30|11:22
pwm_output.d3.32 kB2014-09-30|11:22
pwm_output.o490.34 kB2014-09-30|11:22
quadrotor.crf458.90 kB2014-09-30|11:22
quadrotor.d3.26 kB2014-09-30|11:22
quadrotor.o502.92 kB2014-09-30|11:22
sd_init.crf421.82 kB2014-09-30|11:22
sd_init.d1.83 kB2014-09-30|11:22
sd_init.o464.06 kB2014-09-30|11:22
spi3.crf452.77 kB2014-09-30|11:22
spi3.d2.79 kB2014-09-30|11:22
spi3.o479.34 kB2014-09-30|11:22
startup_stm32f4xx.d59.00 B2014-09-30|11:21
startup_stm32f4xx.o7.73 kB2014-09-30|11:21
stm32adc.crf416.63 kB2014-09-30|11:21
stm32adc.d1.84 kB2014-09-30|11:21
stm32adc.o444.02 kB2014-09-30|11:21
stm32f4xx_adc.crf422.59 kB2014-09-30|11:21
stm32f4xx_adc.d2.01 kB2014-09-30|11:21
stm32f4xx_adc.o487.58 kB2014-09-30|11:21
stm32f4xx_dbgmcu.crf415.63 kB2014-09-30|11:21
stm32f4xx_dbgmcu.d2.12 kB2014-09-30|11:21
stm32f4xx_dbgmcu.o440.03 kB2014-09-30|11:21
stm32f4xx_dcmi.crf417.75 kB2014-09-30|11:21
stm32f4xx_dcmi.d2.04 kB2014-09-30|11:21
stm32f4xx_dcmi.o453.16 kB2014-09-30|11:21
stm32f4xx_dma.crf422.48 kB2014-09-30|11:21
stm32f4xx_dma.d2.01 kB2014-09-30|11:21
stm32f4xx_dma.o461.39 kB2014-09-30|11:21
stm32f4xx_exti.crf416.59 kB2014-09-30|11:21
stm32f4xx_exti.d2.04 kB2014-09-30|11:21
stm32f4xx_exti.o444.07 kB2014-09-30|11:21
stm32f4xx_flash.crf420.54 kB2014-09-30|11:21
stm32f4xx_flash.d2.08 kB2014-09-30|11:21
stm32f4xx_flash.o475.34 kB2014-09-30|11:21
stm32f4xx_gpio.crf417.89 kB2014-09-30|11:21
stm32f4xx_gpio.d2.04 kB2014-09-30|11:21
stm32f4xx_gpio.o453.07 kB2014-09-30|11:21
stm32f4xx_it.crf415.49 kB2014-09-30|11:21
stm32f4xx_it.d1.97 kB2014-09-30|11:21
stm32f4xx_it.o444.81 kB2014-09-30|11:21
stm32f4xx_pwr.crf417.44 kB2014-09-30|11:21
stm32f4xx_pwr.d2.01 kB2014-09-30|11:21
stm32f4xx_pwr.o449.88 kB2014-09-30|11:21
stm32f4xx_rcc.crf424.55 kB2014-09-30|11:21
stm32f4xx_rcc.d2.01 kB2014-09-30|11:21
stm32f4xx_rcc.o495.22 kB2014-09-30|11:21
stm32f4xx_rng.crf415.92 kB2014-09-30|11:21
stm32f4xx_rng.d2.01 kB2014-09-30|11:21
stm32f4xx_rng.o443.76 kB2014-09-30|11:21
stm32f4xx_rtc.crf433.11 kB2014-09-30|11:21
stm32f4xx_rtc.d2.01 kB2014-09-30|11:21
stm32f4xx_rtc.o516.53 kB2014-09-30|11:21
stm32f4xx_sdio.crf419.94 kB2014-09-30|11:21
stm32f4xx_sdio.d2.04 kB2014-09-30|11:21
stm32f4xx_sdio.o474.00 kB2014-09-30|11:21
stm32f4xx_spi.crf420.43 kB2014-09-30|11:21
stm32f4xx_spi.d2.01 kB2014-09-30|11:21
stm32f4xx_spi.o468.64 kB2014-09-30|11:21
stm32f4xx_syscfg.crf416.09 kB2014-09-30|11:21
stm32f4xx_syscfg.d2.12 kB2014-09-30|11:21
stm32f4xx_syscfg.o441.90 kB2014-09-30|11:21
stm32f4xx_tim.crf435.53 kB2014-09-30|11:21
stm32f4xx_tim.d2.01 kB2014-09-30|11:21
stm32f4xx_tim.o563.30 kB2014-09-30|11:21
stm32f4xx_usart.crf420.95 kB2014-09-30|11:21
stm32f4xx_usart.d2.08 kB2014-09-30|11:21
stm32f4xx_usart.o474.46 kB2014-09-30|11:21
stm32f4xx_wwdg.crf416.16 kB2014-09-30|11:21
stm32f4xx_wwdg.d2.04 kB2014-09-30|11:21
stm32f4xx_wwdg.o443.88 kB2014-09-30|11:21
system_stm32f4xx.crf417.16 kB2014-09-30|11:21
system_stm32f4xx.d2.06 kB2014-09-30|11:21
system_stm32f4xx.o438.50 kB2014-09-30|11:21
uart1.crf455.77 kB2014-09-30|11:22
uart1.d2.97 kB2014-09-30|11:22
uart1.o490.19 kB2014-09-30|11:22
ultrasonic.crf420.98 kB2014-09-30|11:22
ultrasonic.d2.09 kB2014-09-30|11:22
ultrasonic.o451.47 kB2014-09-30|11:22
usart1dmatx.crf418.27 kB2014-09-30|11:22
usart1dmatx.d2.02 kB2014-09-30|11:22
usart1dmatx.o444.86 kB2014-09-30|11:22
Protel76.01 kB2013-11-26|21:29
01.97 kB
startup_stm32f4xx.s28.82 kB2011-10-28|10:31
system_stm32f4xx.c21.36 kB2013-06-17|19:09
system_stm32f4xx.h2.05 kB2011-10-28|10:31
startup_stm32f4xx.lst73.83 kB2014-09-30|11:21
01.97 kB
main.c9.82 kB2014-02-27|11:56
main.h1.86 kB2012-11-15|11:46
Read_Me.txt6.96 kB2013-12-16|21:46
stm32f4xx_conf.h3.71 kB2013-03-05|14:42
stm32f4xx_it.c4.34 kB2013-03-05|12:05
stm32f4xx_it.h2.00 kB2013-03-05|12:06
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